IBM announces sub-1nm transistor technology to improve chip performance
IBM has unveiled a new NanoStack architecture that allows for the creation of transistors smaller than one nanometer. The technology is designed to increase processing power while significantly reducing energy consumption.
Amalgamated from Live Science (opens in new tab), Ars Technica (opens in new tab), Live Science (opens in new tab)
IBM has announced the development of a sub-1nm transistor architecture known as NanoStack, which enables the production of computer chips with dimensions smaller than one nanometer. According to reports from Live Science, this advancement allows for the integration of 100 billion transistors onto a single chip approximately the size of a fingernail.
The move toward sub-1nm technology is intended to address current limitations in semiconductor manufacturing. Reports from both Live Science and Ars Technica indicate that the NanoStack design aims to provide more efficient and powerful hardware for various computing applications.
Technical performance data cited by Live Science shows that these chips can deliver 50 percent better performance while consuming 70 percent less energy than current-generation models. The development is framed as a significant step in maintaining Moore's Law, which has historically guided the steady increase of transistor density on integrated circuits.
Ars Technica notes that the primary goals for this new technology are to improve both power efficiency and overall computing speed. By moving to this smaller scale, the company aims to provide higher performance capabilities for future hardware generations.